^{2}CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver

^{2}reconfigurable sigma delta CAD para receptor móvil WiMAX

^{a}

^{a}Corresponding author. E-mail:

^{2}CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver,”

WiMAX (Worldwide Interoperability for Microwave Access) embodies the IEEE 802.16 family of standards that provision wireless broadband access. With the IEEE 802.16e−2005 mobility amendment, WiMAX promises to address the ever-increasing demand for mobile high-speed wireless data in fourth-generation (4G) networks

With the development of wireless communication systems, there has been increasing demand for low cost and low power ADCs. ΣΔ ADCs are ideally suited to such applications. In fact, while oversampling ADCs have proven useful in high resolution and wide frequency applications, Nyquist ADCs are more competitive for these applications

The need for low power ADC is increasing as CMOS technology is scaling down. CT ΣΔ ADCs promise lower power consumption than discrete-time ADCs

The remainder of this paper is organized as follows. The reconfigurable CT ΣΔ ADC architecture is described in the next section. Then, we address the reconfigurable ADC implementation and present the post-layout simulation. Finally, the main conclusions of this study are drawn.

The proposed CT ΣΔ ADC architecture is considered for a multi-band and multi-mode system in 5 MHz, 7 MHz or 10 MHz channel bandwidths (BW). It is a reconfigurable and programmable ADC, which aims to optimally cover bandwidth and resolution ranges and to optimize power and area for a specific application using the same ADC architecture. The reconfigurable ADC is based on bandwidth reconfiguration by dynamically adapting a sampling frequency and an over-sampling ratio (OSR)

The purpose of our design technique is to keep a specific ΣΔ ADC architecture in response the multi-band and multi-mode aspects of the WiMAX standard. To this end, we set each sampling frequency corresponding to each channel bandwidth, so that we keep the same OSR value for each channel bandwidth. Moreover, we use a single-bit quantizer for each channel bandwidths. This technique is intended to optimize power and area compared to ΣΔ ADCs that consist of two or three cascaded stages

The over-sampling ratio is given by:

Where F_{s} is the sampling frequency and F_{b} is the signal bandwidth. The theoretical modulator signal-to-noise ratio is expressed as

Where L, OSR and n are the ADC order, the over-sampling ratio and the quantizer bitness, respectively.

To increase immunity to interferences, a reconfigurable CT ΣΔ ADC with a feedback loop architecture should be used since its signal transfer function (STF) has a faster roll-off in out-of-channel frequencies in comparison to feedforward loop architectures

We used the pole placement method introduced in _{1} and dt_{2}) and looping D.

The analytical expression of the linearized noise shaping transfer function can be written as:

Where w_{p} is the cut-off frequency and the gain K of the linearized model is set to one for calculation of the loop coefficients. Moreover, to numerically calculate the loop coefficients, it is sufficient to select the desired CT ΣΔ noise shaping. The Butterworth or Chebyshev filtering functions are often preferred. Knowing the analytical expression of the linearized NTF and the desired pole position, it becomes easy to calculate the corresponding loop coefficients. The coefficients optimized with the pole placement method are summarized in

Deviation of the CT filter coefficients can affect the ADC signal-to-noise ratio. _{1}, a_{2}, a_{3}, a_{4} and D) for 5 MHz channel bandwidth. Obviously, at E = 0, the SNR is at the maximum.

The system becomes less stable when the error of the CT filter coefficients exceeds ±10%, representing the tolerable error limit, which proves the robustness of the pole placement method.

The loop filter utilizing CT ΣΔ ADC was achieved with an active-RC op-amp circuit as shown in

The CT ΣΔ ADC operates with three different sampling frequencies, which are applied to the two D latches and the comparator. Thus, each sampling frequency corresponds to these RC integration constants. For this reason, we used variable capacitances. Each integrator capacitance is made up of two capacitances sum C_{a} and C_{b}. In fact, C_{a} and C_{b} represent the MIM capacitor and variable capacitor, respectively, in an NMOS transistor where the drain and the source are connected together and controlled by the control voltage (V_{ctr}). _{ctr}. Moreover, the capacitor built as a parallel connection of MIM and NMOS gate capacitances versus V_{ctr} is shown in the same figure. The capacitance decreases from 1,22pF to 0,5pF over the V_{ctr} range -1V to 2V.

Given the above overview of the proposed structure, we can easily examine its various blocks in details in the following subsections. In particular, we presented transistor-level performance of the Regulated Telescopic Operational Transconductance Amplifier (OTA), the comparator, and the clock generator.

Several fundamental issues arise when selecting an optimal architecture for the OTA circuit. This choice aims at achieving both large gain and a large bandwidth performance. We used the Regulated Telescopic OTA instead of the Telescopic OTA in order to obtain increased DC gain without changing the gain-bandwidth product (GBW). In fact, the Regulated Telescopic OTA is a version of the simple Telescopic circuit with the gate voltage of the cascade transistor being controlled by a feedback amplifier

The open loop gain (A_{V}) for the Regulated Telescopic OTA circuit and the GBW are given respectively by the following equations:

Where g_{mi} is the transconductance of M_{i} transistor for I = (1, 4, 5, 10), ro_{i} is the drain-source resistance of Mi transistor for i = (1, 4, 5, 7, 9, 10), C_{GD2}, C_{DB2} and CL are the drain gate capacitance, the bulk drain capacitance of the M_{2} transistor and the load capacitance at the output node, respectively.

According to

Where q is the quantization step of the CT ΣΔ ADC. It is calculated as follows:

Where the ADC full scale level (V_{Full_scale}) is equal to 13 dBm and the ADC resolution (N) is equal to 11bits _{v} is greater than 60 dB. In

The output frequency response of the Regulated Telescopic OTA is plotted in

A latched comparator was used here to act as a single-bit quantizer to convert an analog signal into a digital signal

Post-layout simulation of the latched comparator verified that the propagation delay was approximately 1,2 ns, 1,16 ns and 1,1 ns for 125 MHz, 175 MHz, and 250 MHz clock frequencies, respectively, and the power consumption was only 16 µW. Additionally, the latched comparator occupied a layout area of (72 × 62)µm^{2}.

The CMOS ring oscillator architecture is made up of five stages of inverters in series separated by capacitors and looped between each structure ^{2}.

The oscillating frequency (f_{osc}) is given by the following equation:

Where n is the number of stages, tp_{HL} is the fall time and tp_{LH} is the rise time. Further, tp_{HL} and tp_{LH} are given respectively in

Where K_{P} and K_{N} are the intrinsic transconductance of the PMOS and NMOS transistors, respectively, and C is the value of the variable capacitor. In fact, the variable capacitor C is an NMOS transistor whose drain and source were connected together and controlled by the control voltage (V_{ctr}). _{ctr}. The oscillating frequency varies from 98 MHz to 304 MHz over the V_{ctr} range -1 V to 2 V.

The integrator represents the main building block in CT ΣΔ ADC. The transfer function of the CT integrator used in

For i = (1, 2, 3, 4), where T’_{S} has a nominal value of T_{S}, the system clock period. If the integrator time k_{i}/T’_{S} deviates from its nominal value, the SNR performance degrades. For this to be proven, _{S}/T_{S}, the normalized time constant, and the y axis is the post-layout simulated flexible ADC SNR. The CT ΣΔ ADC becomes less stable when the RC time constant decreases below 0,8 and increases above 1,2.

The proposed reconfigurable fourth-order CT ΣΔ ADC was implemented in AMS 0,35μm CMOS process and simulated using the Cadence tool. The reconfigurable ADC samples the signals at 125 MHz, 175 MHz and 250 MHz with respectively 5 MHz, 7 MHz and 10 MHz channel bandwidths, respectively, and the total power consumption is 28 mW, 28,2 mW and 28,6 mW, respectively. The layout of the reconfigurable ADC is shown in ^{2}, including bonding pads.

The post-layout simulation output spectrum of the reconfigurable fourth-order CT ΣΔ ADC for 5 MHz, 7 MHz and 10 MHz channel bandwidths, at a sampling frequencies of 125 MHz, 175 MHz and 250 MHz, respectively, with 16384 samples and an OSR of 25 is shown in

The SNR versus input signal amplitude over a 5 MHz channel bandwidth was analyzed in different process corners and temperature variations such as TT at 27 °C, TT at 100 °C, FF at 0 °C and SS at 100 °C. The results for all process corners and temperature variations are shown in

In this work, the design of a fourth-order reconfigurable CT ΣΔ ADC intended for use in the mobile WiMAX standard was achieved. Our design technique aimed at keeping a specific ADC architecture in response to multi-band and multi-mode aspects of the mobile WiMAX standard for 5 MHz, 7 MHz and 10 MHz channel bandwidths. For this reason, a sampling frequency was set for each channel bandwidth so that the same OSR value was kept for different channel bandwidths. In addition, the pole placement method was used to calculate the optimized coefficients of the CT filter. Both of the architecture and the main building blocks of the fourth-order feedback low-pass CT ΣΔ ADC with a single-bit quantizer were presented and designed. The reconfigurable ADC die chip occupies an area of 0,58 mm2 and achieves 72,89 dB, 67,26 dB and 66,47 dB peak SNR values. The power consumption is approximately equal to 28 mW using a 3,3 V supply voltage.

Research article.