Introduction

WiMAX (Worldwide Interoperability for Microwave Access) embodies the IEEE 802.16 family of standards that provision wireless broadband access. With the IEEE 802.16e−2005 mobility amendment, WiMAX promises to address the ever-increasing demand for mobile high-speed wireless data in fourth-generation (4G) networks [1], [2]. In addition, mobile broadband wireless networks, such as mobile WiMAX, have been designed to support several features, incliding quality of service or enhanced data protection mechanisms, in order to provide true access to real-time multimedia applications [3]. Further, mobile WiMAX uses a new physical layer radio access technology called Orthogonal Frequency Division Multiple Access (OFDMA) as the multiplexing technique in uplink and downlink [4].

With the development of wireless communication systems, there has been increasing demand for low cost and low power ADCs. ΣΔ ADCs are ideally suited to such applications. In fact, while oversampling ADCs have proven useful in high resolution and wide frequency applications, Nyquist ADCs are more competitive for these applications [5]. In addition, the input signal to the ΣΔ ADC is oversampled at a much higher frequency than the Nyquist rate. “This means that the effective bandwidth of the signal constitutes a negligible portion of the whole band. Noise shaping techniques are used to reduce the power spectrum of noise in the effective bandwidth of the signal.” Note that in this case, the quantization error is also treated as noise. Several implementations of the discrete-time and continuous-time ΣΔ ADCs have been presented in the literature [6], [7].

The need for low power ADC is increasing as CMOS technology is scaling down. CT ΣΔ ADCs promise lower power consumption than discrete-time ADCs [8]. In addition, a CT ΣΔ ADC is an attractive choice of ADC implementation as it possesses inherent anti- aliasing filter characteristics and relaxed requirements on integrators, thus eliminating the need for additional filtering and sampling circuitry, thus mitigating power consumption. They also do not require complex switching and clocking mechanism, thus paving the way for very high OSR [9]. However, they are less robust against jitter effects and excess loop delay compared with their discrete-time counterparts [10]. For this reason, we proposed a fourth-order reconfigurable CT ΣΔ ADC intended for use in the mobile WiMAX standard. In addition, our design technique aims to maintain a specific ADC architecture in response to the multi-mode and multi-band aspects of the mobile WiMAX standard.

The remainder of this paper is organized as follows. The reconfigurable CT ΣΔ ADC architecture is described in the next section. Then, we address the reconfigurable ADC implementation and present the post-layout simulation. Finally, the main conclusions of this study are drawn.

The Proposed Reconfigurable CT ΣΔ ADC Architecture

The proposed CT ΣΔ ADC architecture is considered for a multi-band and multi-mode system in 5 MHz, 7 MHz or 10 MHz channel bandwidths (BW). It is a reconfigurable and programmable ADC, which aims to optimally cover bandwidth and resolution ranges and to optimize power and area for a specific application using the same ADC architecture. The reconfigurable ADC is based on bandwidth reconfiguration by dynamically adapting a sampling frequency and an over-sampling ratio (OSR) [11]. In fact, the main purpose of our methodology is for designing a reconfigurable CT ΣΔ ADC that efficiently covers varying channel bandwidths by configuring the ADC to the proper architecture for each channel bandwidth.

The purpose of our design technique is to keep a specific ΣΔ ADC architecture in response the multi-band and multi-mode aspects of the WiMAX standard. To this end, we set each sampling frequency corresponding to each channel bandwidth, so that we keep the same OSR value for each channel bandwidth. Moreover, we use a single-bit quantizer for each channel bandwidths. This technique is intended to optimize power and area compared to ΣΔ ADCs that consist of two or three cascaded stages [12].

The over-sampling ratio is given by:

Where F_s is the sampling frequency and F_b is the signal bandwidth. The theoretical modulator signal-to-noise ratio is expressed as [13]:

Where L, OSR and n are the ADC order, the over-sampling ratio and the quantizer bitness, respectively.

To increase immunity to interferences, a reconfigurable CT ΣΔ ADC with a feedback loop architecture should be used since its signal transfer function (STF) has a faster roll-off in out-of-channel frequencies in comparison to feedforward loop architectures [14]. The stabilization of the modulator transfer function is performed by using a loopback input at each filter stage [15]. A conventional fourth-order feedback low-pass CT ADCs with a single-bit quantizer is shown in figure 1 [16]. The proposed CT ΔΣ ADC architecture consists of a mono-bit quantizer, operating at 125 MHz, 175 MHz and 250 MHz with an OSR of 25.

We used the pole placement method introduced in [17], a linearization technique of CT ΣΔ loop, to calculate and analyze the noise shaping transfer function (NTF) of the CT ADC according to the loop gain variation. This method aims to calculate the optimized coefficients of the CT filter to achieve desired noise shaping. The block diagram describing the architecture of fourth-order feedback ΣΔ ADC is shown in figure 2. As seen this figure, the CT ADC has a delay compensation system for the signal propagation delay in the internal ADC and feedback digital analog converters. The ADC correction system was achieved by introducing two fixed deadlines (dt₁ and dt₂) and looping D.

The analytical expression of the linearized noise shaping transfer function can be written as:

Where w_p is the cut-off frequency and the gain K of the linearized model is set to one for calculation of the loop coefficients. Moreover, to numerically calculate the loop coefficients, it is sufficient to select the desired CT ΣΔ noise shaping. The Butterworth or Chebyshev filtering functions are often preferred. Knowing the analytical expression of the linearized NTF and the desired pole position, it becomes easy to calculate the corresponding loop coefficients. The coefficients optimized with the pole placement method are summarized in table 1. Table 2 lists the WiMAX ADC specifications.

Deviation of the CT filter coefficients can affect the ADC signal-to-noise ratio. Figure 3 depicts the ADC SNR deviations versus the errors (E) of the CT filter coefficients (a₁, a₂, a₃, a₄ and D) for 5 MHz channel bandwidth. Obviously, at E = 0, the SNR is at the maximum.

The system becomes less stable when the error of the CT filter coefficients exceeds ±10%, representing the tolerable error limit, which proves the robustness of the pole placement method.

Design Method of the Reconfigurable CT ΣΔ ADC

The loop filter utilizing CT ΣΔ ADC was achieved with an active-RC op-amp circuit as shown in figure 4. This implementation allows the benefits of high linearity, high output signal swing, and a good virtual ground for the digital analog converters (DAC) in the ADC feedback [18]. The CT-filter coefficients are implemented using current-steering DACs with NRZ feedback [19]. The excess loop delay effect is typically a constraint in the CT ΣΔ ADC. Hence, an extra feedback branch between the output and the input to the quantizer (DAC D in figure 4) and two D latches were used in both stages in order to avoid excess loop delay effect [20].

The CT ΣΔ ADC operates with three different sampling frequencies, which are applied to the two D latches and the comparator. Thus, each sampling frequency corresponds to these RC integration constants. For this reason, we used variable capacitances. Each integrator capacitance is made up of two capacitances sum C_a and C_b. In fact, C_a and C_b represent the MIM capacitor and variable capacitor, respectively, in an NMOS transistor where the drain and the source are connected together and controlled by the control voltage (V_ctr). Figure 5 shows the MIM and NMOS gate capacitance values versus V_ctr. Moreover, the capacitor built as a parallel connection of MIM and NMOS gate capacitances versus V_ctr is shown in the same figure. The capacitance decreases from 1,22pF to 0,5pF over the V_ctr range -1V to 2V.

Given the above overview of the proposed structure, we can easily examine its various blocks in details in the following subsections. In particular, we presented transistor-level performance of the Regulated Telescopic Operational Transconductance Amplifier (OTA), the comparator, and the clock generator.

Regulated Telescopic OTA Design

Several fundamental issues arise when selecting an optimal architecture for the OTA circuit. This choice aims at achieving both large gain and a large bandwidth performance. We used the Regulated Telescopic OTA instead of the Telescopic OTA in order to obtain increased DC gain without changing the gain-bandwidth product (GBW). In fact, the Regulated Telescopic OTA is a version of the simple Telescopic circuit with the gate voltage of the cascade transistor being controlled by a feedback amplifier [21]. The feedback is applied around the cascade transistor in order to improve the gain. This feedback is in fact a parallel-series, causing the output impedance to rise with the feedback gain. The gain increases proportionally. Figure 6 shows the Regulated Telescopic OTA circuit. Despite adding a feedback amplifier, the voltage swing of the Regulated Telescopic OTA at the output node was reduced and the layout area increased, compared to the Telescopic OTA.

The open loop gain (A_V) for the Regulated Telescopic OTA circuit and the GBW are given respectively by the following equations:

Where g_mi is the transconductance of M_i transistor for I = (1, 4, 5, 10), ro_i is the drain-source resistance of Mi transistor for i = (1, 4, 5, 7, 9, 10), C_GD2, C_DB2 and CL are the drain gate capacitance, the bulk drain capacitance of the M₂ transistor and the load capacitance at the output node, respectively.

According to [22], we applied the following constraint:

Where q is the quantization step of the CT ΣΔ ADC. It is calculated as follows:

Where the ADC full scale level (V_{Full_scale}) is equal to 13 dBm and the ADC resolution (N) is equal to 11bits [16]. In this case, we assume the overall gain A_v is greater than 60 dB. In [22], it is mentioned that:

The output frequency response of the Regulated Telescopic OTA is plotted in figure 7. The Regulated Telescopic OTA has a DC gain of 66 dB, a large GBW of 862 MHz and a phase margin of 58 degrees. The Regulated Telescopic OTA performance measures are summarized in table 3.

Latched Comparator

A latched comparator was used here to act as a single-bit quantizer to convert an analog signal into a digital signal [23]. Figure 8 depicts the latched comparator architecture where the speed should be adequate to achieve the desired sampling rate, input offset, input referred noise, and hysteresis. The offset and noise at the comparator input would be omitted by the feedback loop of the CT ΣΔ ADC.

Post-layout simulation of the latched comparator verified that the propagation delay was approximately 1,2 ns, 1,16 ns and 1,1 ns for 125 MHz, 175 MHz, and 250 MHz clock frequencies, respectively, and the power consumption was only 16 µW. Additionally, the latched comparator occupied a layout area of (72 × 62)µm².

Clock Generator

The CMOS ring oscillator architecture is made up of five stages of inverters in series separated by capacitors and looped between each structure [24]. The clock generator is used here in order to generate different sampling frequencies for the CT ΣΔ ADC such as 125 MHz, 175 MHz and 250 MHz. Therefore, we used the CMOS ring oscillator architecture with variable capacitors as shown in figure 9. Moreover, the ring oscillator exhibited a rise time of 0,2 ns, a power consumption of 19 µW, and layout area of (70 × 44)µm².

The oscillating frequency (f_osc) is given by the following equation:

Where n is the number of stages, tp_HL is the fall time and tp_LH is the rise time. Further, tp_HL and tp_LH are given respectively in (7) and (8).

Where K_P and K_N are the intrinsic transconductance of the PMOS and NMOS transistors, respectively, and C is the value of the variable capacitor. In fact, the variable capacitor C is an NMOS transistor whose drain and source were connected together and controlled by the control voltage (V_ctr). Figure 10 depicts the oscillating frequency versus V_ctr. The oscillating frequency varies from 98 MHz to 304 MHz over the V_ctr range -1 V to 2 V.

SNR Versus Normalized RC Time Constant

The integrator represents the main building block in CT ΣΔ ADC. The transfer function of the CT integrator used in figure 4 is given by:

For i = (1, 2, 3, 4), where T’_S has a nominal value of T_S, the system clock period. If the integrator time k_i/T’_S deviates from its nominal value, the SNR performance degrades. For this to be proven, figure 11 presents the post-layout simulated SNR performance of the Flexible CT ΣΔ ADC versus the normalized RC time constant associated with the loop filter. The x axis is T’_S/T_S, the normalized time constant, and the y axis is the post-layout simulated flexible ADC SNR. The CT ΣΔ ADC becomes less stable when the RC time constant decreases below 0,8 and increases above 1,2.

Post-Layout Simulation Results

The proposed reconfigurable fourth-order CT ΣΔ ADC was implemented in AMS 0,35μm CMOS process and simulated using the Cadence tool. The reconfigurable ADC samples the signals at 125 MHz, 175 MHz and 250 MHz with respectively 5 MHz, 7 MHz and 10 MHz channel bandwidths, respectively, and the total power consumption is 28 mW, 28,2 mW and 28,6 mW, respectively. The layout of the reconfigurable ADC is shown in figure 12. This occupies an area of (1,14 × 0,47)mm², including bonding pads.

The post-layout simulation output spectrum of the reconfigurable fourth-order CT ΣΔ ADC for 5 MHz, 7 MHz and 10 MHz channel bandwidths, at a sampling frequencies of 125 MHz, 175 MHz and 250 MHz, respectively, with 16384 samples and an OSR of 25 is shown in figure 13. It reveals the SNR values of approximately 71,47 dB, 67,24 dB and 66,37 dB, over channel bandwidths of 5 MHz, 7 MHz and 10 MHz, respectively. In addition, figure 13 provides transistor level SNR values of approximately 74,8 dB, 71 dB and 70 dB, over channel bandwidths of 5 MHz, 7 MHz and 10 MHz respectively.

Figure 14 shows the SNR versus input signal amplitude over 5 MHz, 7 MHz and 10 MHz channel bandwidths. The reconfigurable CT ΣΔ ADC achieves 72,89 dB, 67,26 dB and 66,47 dB peak SNR and 73,5 dB, 69,47 dB and 66,5 dB dynamic range, respectively. The signal-to-noise and distortion ratio (SNDR) versus input signal amplitude is shown in figure 15. It reveals peak SNDR values of 70,79 dB, 64,96 dB and 64,27 dB over channel bandwidths of 5 MHz, 7 MHz and 10 MHz, respectively. The flexible CT ΣΔ ADC performances measures are listed in table 4. Table 5 summarizes the performance of the proposed reconfigurable CT ΣΔ ADC in comparison with other CT ΣΔ ADCs presented recently. Relying on this comparison table, the proposed CT ΣΔ ADC achieves a small FOM of approximately 1,98 pJ/Conv, 2,21 pJ/Conv and 2,43 pJ/Conv over channel bandwidths of 5 MHz, 7 MHz and 10 MHz, respectively.

The SNR versus input signal amplitude over a 5 MHz channel bandwidth was analyzed in different process corners and temperature variations such as TT at 27 °C, TT at 100 °C, FF at 0 °C and SS at 100 °C. The results for all process corners and temperature variations are shown in figure 16. The SS corner at 100 °C gives the worst result where, the peak SNR dropped to approximately 4,7 dB.

Conclusions

In this work, the design of a fourth-order reconfigurable CT ΣΔ ADC intended for use in the mobile WiMAX standard was achieved. Our design technique aimed at keeping a specific ADC architecture in response to multi-band and multi-mode aspects of the mobile WiMAX standard for 5 MHz, 7 MHz and 10 MHz channel bandwidths. For this reason, a sampling frequency was set for each channel bandwidth so that the same OSR value was kept for different channel bandwidths. In addition, the pole placement method was used to calculate the optimized coefficients of the CT filter. Both of the architecture and the main building blocks of the fourth-order feedback low-pass CT ΣΔ ADC with a single-bit quantizer were presented and designed. The reconfigurable ADC die chip occupies an area of 0,58 mm2 and achieves 72,89 dB, 67,26 dB and 66,47 dB peak SNR values. The power consumption is approximately equal to 28 mW using a 3,3 V supply voltage.

References

Notes

* Research article.

Author notes

^a Corresponding author. E-mail: jihenemallek@yahoo.fr

Additional information

How to cite this article: J. Mallek, H. Daoud, R. Aloulou, H. Mnif, and M. Loulou, “A 0,58 mm² CMOS reconfigurable sigma delta ADC for mobile WiMAX receiver,” Ing. Univ. vol. 23, no. 1, 2019 [Online]. https://doi.org/10.11144/Javeriana.iyu23-1.crsd

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