RS Decoder (255,k) in Reconfigurable Hardware Oriented Towards Cognitive Radio
##plugins.themes.bootstrap3.article.details##
This paper presents the parametric configuration of a Reed Salomon decoder through VHDL hardware description language, oriented towards cognitive radio applications, on FPGA circuits, which support the reconfiguration of the hardware. Using a parameter selection module designed in VHD Land modular architecture, with phase concatenation and enabling signals, it is possible to configure in the hardware the number of information symbols in the RS(255,k)’s, given that suchde coders are widely used in different communication protocols. In the decoder design a model was established based on the architecture of its components; we carried out simulations and the estimation of resource consumption, enabled by the ISE 11 Xilinx tool, and we studied the resulting schematics, with which we were able to validate the performance and logic of the created circuit. In this way we obtained a reconfigurable design based on a model of phase enabling, which offers a high efficiency ratere garding synthesis resources.
Reed Solomon decoder, reconfigurable, VHDL, FPGA, cognitive radioCodificador Reed Solomon, reconfigurable, VHDL, FPGA, radio cognitivo
ALAUS, L.; NOGUET, D. y PALICOT, J. A reconfigurable LFSR for tri-standard SDR transceiver, architecture and complexity analysis. Proceedings of 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. 2008, pp. 61-67.
AL GHOUWAYEL, A.; LOUET, Y. y PALICOT, J. A reconfigurable architecture for the FFT operator in a software radio context. IEEE International Symposium on Circuits and Systems, 2006.
ALTERA. RS Encoder. 2011 [documento en línea].
ASTARLOA, A. Reconfiguración dinámica de sistemas modulares multi-procesador en dispositivos SoPC. s. l.: Universidad del País Vasco, 2005.
ATIENO, L.; ALLEN, J.; GOECKEL, D. y TESSIER, R. An adaptive Reed-Solomon errorsand-erasures decoder [documento en línea]. Proceedings ACM/SIGDA 14th International symposium on Field programmable gate arrays. 2006, pp. 150-158.
BLUST M., S. Software defined radio enabling technologie. New York: Wiley, 2002.
CENDITEL. Proyecto hardware libre [documento en línea], 2012.
FETTE, B. Cognitive radio tecnology. 2nd. ed. Philadelphia: Academic Press-Elsevier, 2009.
FITZEK, F. H. P. Cooperation in wireless networks, principles and applications: real egoistic behavior is to cooperate. New York: Kluwer, 2006.
FLOCKE, A. et al. Implementación y modelado de parametrizables decodificadores de alta velocidad Reed Solomon en FPGAs. Advances in Radio Science. 2005, vol. 3, núm. 14, pp. 271-276 [documento en línea].
GIANNI, P.; CLAUDIO, G. D. y CORTEGGIANO, F. Implementación en FPGA de un código Reed Solomon RS (255,239). Actas de la Escuela Argentina de Microelectrónica, Tecnología yAplicaciones. 2007, vol. 3, pp. 77-81 [documento en línea].
JINZHOU, Z.; XIANFENG, L.; ZHUGANG, W. y WIEMING, X. The design of a RS encoder. Future Computing, Communication, Control and Management. 2012, vol. 144, pp. 87-91.
JONDRAL, F. Software defined radio enabling technologie: A technique for SDR Implementation. New York: Wiley, 2002.
LATTICE, S. C. Dynamic block Reed-Solomon encoder, 2005 [documento en línea].
SANDOVAL RUIZ, C. Codificador RS(n,k) basado en LFCS: caso de estudio RS(7,3). Revista de la Facultad de Ingeniería de la Universidad de Antioquia. 2012, núm. 64, pp. 45-55.
SANDOVAL RUIZ, C. Modular programming of functions for turbo product codes on FPGA. Revista Técnica de la Facultad de Ingeniería, Universidad del Zulia. 2008, vol. 31, núm. 3, pp. 294-301 [documento en línea].
SANDOVAL RUIZ, C. Multiplicador paralelo en campos finitos de Galois GF (2m) aplicado a códigos Reed Solomon con longitud ajustable sobre FPGA. Congreso Internacional de Investigación UC, 2010.
SANDOVAL RUIZ, C. E. y FEDÓN, A. Codificador y decodificador digital Reed-Solomon programados para hardware reconfigurable. Ingeniería y Universidad. 2007, vol. 11, núm. 1, pp. 17-32 [documento en línea].
SUTTER, G. y BOEMO, E. Experiments in low power FPGA design. Latin American Applied Research. 2007, vol. 37, núm. 1, pp. 99-104.
TONFAT, J. y SILVA, C. Diseño de un modulador FM basado en la tecnología software Radio. XIV Iberchip Workshop, México, 2008
XILINX. IPCore RS Encoder 7.1, 2011 [documento en línea]
XILINX, IPCore RS Encoder 8.0, 2012 [documento en línea]