Published Apr 17, 2013



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Cecilia Esperanza Sandoval-Ruiz, PhD

Antonio Fedón-Rovira, MSc

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Abstract

This paper presents the parametric configuration of a Reed Salomon decoder through VHDL hardware description language, oriented towards cognitive radio applications, on FPGA circuits, which support the reconfiguration of the hardware. Using a parameter selection module designed in VHD Land modular architecture, with phase concatenation and enabling signals, it is possible to configure in the hardware the number of information symbols in the RS(255,k)’s, given that suchde coders are widely used in different communication protocols. In the decoder design a model was established based on the architecture of its components; we carried out simulations and the estimation of resource consumption, enabled by the ISE 11 Xilinx tool, and we studied the resulting schematics, with which we were able to validate the performance and logic of the created circuit. In this way we obtained a reconfigurable design based on a model of phase enabling, which offers a high efficiency ratere garding synthesis resources.

Keywords

Reed Solomon decoder, reconfigurable, VHDL, FPGA, cognitive radioCodificador Reed Solomon, reconfigurable, VHDL, FPGA, radio cognitivo

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How to Cite
Sandoval-Ruiz, C. E., & Fedón-Rovira, A. (2013). RS Decoder (255,k) in Reconfigurable Hardware Oriented Towards Cognitive Radio. Ingenieria Y Universidad, 17(1), 77-92. https://doi.org/10.11144/Javeriana.iyu17-1.rdrh
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